1. Field of the Invention
The invention relates generally to audio amplification systems, and more particularly to systems and methods for transferring data across clock domains, wherein the data transfer is tolerant of variations in the clock signals of the different clock domains.
2. Related Art
Pulse Width Modulation (PWM) or Class D signal amplification technology has existed for a number of years. PWM technology has become more popular with the proliferation of Switched Mode Power Supplies (SMPS). Since this technology emerged, there has been an increased interest in applying PWM techniques in signal amplification applications as a result of the significant efficiency improvement that can be realized through the use of Class D power output topology instead of the legacy (linear Class AB) power output topology.
Early attempts to develop signal amplification applications utilized the same approach to amplification that was being used in the early SMPS. More particularly, these attempts utilized analog modulation schemes that resulted in very low performance applications. These applications were very complex and costly to implement. Consequently, these solutions were not widely accepted. Prior art analog implementations of Class D technology have therefore been unable to displace legacy Class AB amplifiers in mainstream amplifier applications.
Recently, digital PWM modulation schemes have surfaced. These schemes use Sigma-Delta modulation techniques to generate the PWM signals used in the newer digital Class D implementations. These digital PWM schemes, however, did little to offset the major barriers to integration of PWM modulators into the total amplifier solution. Class D technology has therefore continued to be unable to displace legacy Class AB amplifiers in mainstream applications.
One of the problems that exists in PWM amplifier systems is that the generation of PWM signals is relatively slow. In one system, for example, a PWM amplifier is implemented using a digital signal processor (DSP) that operates at 150 MHz. It may, however, be desirable to provide output at a higher rate than 150 MHz. Because the this conversion from the lower rate (150 MHz) to the higher rate (e.g., 300 MHz) involves audio data, it must be performed in real time in order to provide acceptable performance.
Another problem with existing systems is that it is typically very difficult to cross from one clock domain to another without having to use very precise tolerances.
If manufactured devices are not within these tolerances, the clock signals in the different domains may vary and cause the domain crossing mechanism to fail. Variations in the clock signals may arise from changes in temperature, drifting voltages, noise, and the like. If the clock signals vary enough, the data that is passed from one domain to another may be corrupted.
It would therefore be desirable to provide a mechanism for transferring data from one clock domain to another in a manner that does not require very strict tolerances, but is adaptable to variations in the clock signals of the different clock domains.